Embodiments of the present invention relate to a multi-phase clock generation circuit that generates a plurality of internal clocks having a plurality of phases.
Recently, in order to achieve high speed operation of a semiconductor memory device, a plurality of internal clocks having a plurality of phases that inputs/outputs data is utilized. For example, a method has been proposed in which four internal clocks having a phase difference of 90° therebetween are generated and used for data input/output to achieve high speed operation, compared with when data is inputted/outputted according to one external clock.
The multi-phase internal clocks may be generated using a plurality of D flip-flops. In order to generate two internal clocks having phases of 0° and 90°, respectively, two D flip-flops and inverters are required, and in order to generate two internal clocks having phases of 180° and 270°, respectively, two D flip-flops and inverters are separately required. However, for the internal clocks generated using the D flip-flops, a margin required for the high speed operation of the semiconductor memory device may not be sufficiently ensured due to an internal time delay that propagates through the D flip-flops and the inverters. Thus, since data may not be inputted/outputted at proper times, a normal operation of the semiconductor memory device may not occur.